TLM-Driven Design And Verification—Time For A Methodology Shift
While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced...
View ArticleThe Integrated IP Subsystem: A Converging SoC Solution
The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a...
View ArticleThe Week In Review: Feb. 8
By Ed Sperling Cadence signed an agreement to buy Bangalore, India-based Cosmic Circuits in a clear bid to grow its IP portfolio. With the acquisition Cadence strengthens its already strong position in...
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Surprises Abound As Subsystem IP Gains Prominence
By John Blyler What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research...
View ArticleThe Week In Review: March 8
By Ed Sperling Politicians are focusing on Silicon Valley once again, using the recent spate of growth as context to discuss education, immigration and infrastructure improvement. Political careers are...
View ArticleHow Much Consolidation Is The Right Amount?
By Ed Sperling Top EDA executives came down firmly on the side of customer choice yesterday evening, laying out reasons and statistics why consolidation has practical limits in EDA. But as the industry...
View ArticleExecutive Briefing: Wally Rhines
By Ed Sperling System-Level Design, as part of its ongoing executive briefing series, sat down with Wally Rhines, Mentor Graphics’ chairman and CEO, to talk about future problems, opportunities, and...
View ArticleThe Week In Review: April 5
By Ed Sperling Mentor Graphics rolled out an IEEE 1801 UPF-based low-power verification flow that spans everything from IP to systems. Considering the growing percentage of third-party IP in designs,...
View ArticleFaster IP Integration
By Ed Sperling System-Level Design sat down with Laurent Moll, chief technology officer at Arteris, to talk about interoperability, complexity and integration issues. What follows are excerpts of that...
View ArticleTaking Aim At Big Data
By Ed Sperling As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries. How successful they are...
View ArticleIP Play
Cadence Senior Vice President Martin Lund talks about the future of IP, why his company has been on an IP acquisition binge, and the new focus on mass-customization. Click here to view the embedded...
View ArticleThe X Factor
By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market...
View ArticleFinFET Technology
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this...
View ArticleExperts At The Table: The Internet Of Everything
By Ed Sperling System-Level Design sat down to discuss the Internet of Things with Jack Guedj, president and CEO of Tensilica; John Heinlein, vice president of marketing for the physical IP division of...
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Experience Required
By John Blyler Many prominent semiconductor, EDA and IP companies are acknowledging the influence of user-experience design methodologies and technologies on their business. Experiences are the...
View ArticleThe Week In Review: May 31
By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for...
View ArticleBlog Review: June 19
By Ed Sperling Cadence’s Brian Fuller talks with Chris Rowen, Tensilica’s CTO and now a Cadence fellow, about what EDA needs to do to reach its full potential. This sounds a lot like Apple’s recent...
View ArticleFrom Design to Test: Developing High-Reliability MTP NVM
In developing high-quality and reliable MTP NVM, NVM IP providers must account for design and architectural considerations as well as comprehensive silicon testing. To help system-on-chip (SoC)...
View ArticleDe-Mystifying The SoC Supply Chain
By Barbara Jorgensen At the heart of every supply chain operation is the desire to mitigate risk. In theory, a supply chain allows a customer to leverage the best of the best in technology, logistics...
View ArticleThe Week In Review: June 28
By Ed Sperling Mentor Graphics added embedded memories to its cell characterization and analysis platform, addressing a growing challenge of excessive runtimes in large circuits. The automated flow...
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